SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Event Trigger Force Register
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| Instance Name | Physical Address |
|---|---|
| EPWM0 | 2300 003Ah |
| EPWM1 | 2301 003Ah |
| EPWM2 | 2302 003Ah |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | INT | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:1 | RESERVED1 | R | 0h | Reserved |
| 0 | INT | R | 0h | INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless 0h Writing a 0 has no effect. Always reads
back a 0h
1h Writing 1 clears the EPWM_ETFLG[0] INT flag
bit and enable further interrupts pulses to
be generated. |