SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The pin direction register (PDIR) specifies the direction of AXRn, ACLKX, AHCLKX, AFSX, ACLKR, AHCLKR, and AFSR pins as either an input or an output pin. Regardless of the pin function register (PFUNC) setting, each PDIR bit must be set to 1 for the specified pin to be enabled as an output and each PDIR bit must be cleared to 0 for the specified pin to be an input. For example, if the McASP is configured to use an internally-generated bit clock and the clock is to be driven out to the system, the PFUNC bit must be cleared to 0 (McASP function) and the PDIR bit must be set to 1 (an output). When AXRn is configured to transmit, the PFUNC bit must be cleared to 0 (McASP function) and the PDIR bit must be set to 1 (an output). Similarly, when AXRn is configured to receive, the PFUNC bit must be cleared to 0 (McASP function) and the PDIR bit must be cleared to 0 (an input). CAUTION: Writing a value other than 0 to reserved bits in this register may cause improper device operation. The number of serializers is device/instance specific. See device datasheet for the number of serializers supported by each instance. Invalid bit settings are reserved.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 0014h |
| MCASP1 | 02B1 0014h |
| MCASP2 | 02B2 0014h |
| MCASP3 | 02B3 0014h |
| MCASP4 | 02B4 0014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| AFSR | AHCLKR | ACLKR | AFSX | AHCLKX | ACLKX | AMUTE | RESERVED68 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED68 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| AXR | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AXR | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | AFSR | R/W | 0h | Determines if AFSR pin functions as an input or output. 0 Pin functions as input. 1 Pin functions as output. |
| 30 | AHCLKR | R/W | 0h | NOTE: AHCLKR, AHCLKX pins are not available on the SOC pinmux directly, but through a clock routing logic that maps the SOC pins (AUDIO_EXT_REFCLK[1:0]) to the McASP clocks. Therefore, GPIO mode control is not functional for these specific pins. 0 Pin functions as input. 1 Pin functions as output. |
| 29 | ACLKR | R/W | 0h | Determines if ACLKR pin functions as an input or output. 0 Pin functions as input. 1 Pin functions as output. |
| 28 | AFSX | R/W | 0h | Determines if AFSX pin functions as an input or output. 0 Pin functions as input. 1 Pin functions as output. |
| 27 | AHCLKX | R/W | 0h | NOTE: AHCLKR, AHCLKX pins are not available on the SOC pinmux directly, but through a clock routing logic that maps the SOC pins (AUDIO_EXT_REFCLK[1:0]) to the McASP clocks. Therefore, GPIO mode control is not functional for these specific pins. 0 Pin functions as input. 1 Pin functions as output. |
| 26 | ACLKX | R/W | 0h | Determines if ACLKX pin functions as an input or output. 0 Pin functions as input. 1 Pin functions as output. |
| 25 | AMUTE | R/W | 0h | Determines if AMUTE pin functions as an input or output. 0 Pin functions as input. 1 Pin functions as output. |
| 24:16 | RESERVED68 | R | 0h | |
| 15:0 | AXR | R/W | 0h | Determines if AXRn pin functions as an input or output. 0 Pin functions as input. 1 Pin functions as output. |