SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and, if PFUNC = 1 (GPIO function) and PDIR = 1 (output), drives a logic low on the pin. PDCLR is useful for a multitasking system because it allows you to clear to a logic low only the desired pin(s) within a system without affecting other I/O pins controlled by the same McASP. CAUTION: Writing a value other than 0 to reserved bits in this register may cause improper device operation.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 0020h |
| MCASP1 | 02B1 0020h |
| MCASP2 | 02B2 0020h |
| MCASP3 | 02B3 0020h |
| MCASP4 | 02B4 0020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| AFSR | AHCLKR | ACLKR | AFSX | AHCLKX | ACLKX | AMUTE | RESERVED71 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED71 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED71 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED71 | AXR | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | AFSR | R/W | 0h | Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0 No effect. 1 PDOUT[31] bit is cleared to 0. |
| 30 | AHCLKR | R/W | 0h | Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0 No effect. 1 PDOUT[30] bit is cleared to 0. |
| 29 | ACLKR | R/W | 0h | Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0 No effect. 1 PDOUT[29] bit is cleared to 0. |
| 28 | AFSX | R/W | 0h | Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0 No effect. 1 PDOUT[28] bit is cleared to 0. |
| 27 | AHCLKX | R/W | 0h | Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0 No effect. 1 PDOUT[27] bit is cleared to 0. |
| 26 | ACLKX | R/W | 0h | Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0 No effect. 1 PDOUT[26] bit is cleared to 0. |
| 25 | AMUTE | R/W | 0h | Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0 No effect. 1 PDOUT[25] bit is cleared to 0. |
| 24:4 | RESERVED71 | R | 0h | |
| 3:0 | AXR | R/W | 0h | Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0 No effect. 1 PDOUT[n] bit is cleared to 0. |