SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The global control register (GBLCTL) provides initialization of the transmit and receive sections. The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12-8 and ACLKR for bits 4-0). Before GBLCTL is programmed, you must ensure that serial clocks are running. If the corresponding external serial clocks, ACLKX and ACLKR, are not yet running, you should select the internal serial clock source in AHCLKXCTL, AHCLKRCTL, ACLKXCTL, and ACLKRCTL before GBLCTL is programmed. Also, after programming any bits in GBLCTL you should not proceed until you have read back from GBLCTL and verified that the bits are latched in GBLCTL.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 0044h |
| MCASP1 | 02B1 0044h |
| MCASP2 | 02B2 0044h |
| MCASP3 | 02B3 0044h |
| MCASP4 | 02B4 0044h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED73 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED73 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED73 | XFRST | XSMRST | XSRCLR | XHCLKRST | XCLKRST | ||
| R | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED72 | RFRST | RSMRST | RSRCLR | RHCLKRST | RCLKRST | ||
| R | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED73 | R | 0h | |
| 12 | XFRST | R/W | 0h | Transmit frame sync generator reset enable bit. 0 Transmit frame sync generator is reset.
1 Transmit frame sync generator is active.
When released from reset, the transmit
frame sync generator begins counting serial
clocks and generating frame sync as
programmed. |
| 11 | XSMRST | R/W | 0h | Transmit state machine reset enable bit. 0 Transmit state machine is held in reset.
AXRn pin state: If PFUNC[n] = 0 and PDIR[n]
= 1; then the serializer drives the AXRn
pin to the state specified for inactive
time slot (as determined by DISMOD bits in
SRCTL).
1 Transmit state machine is released from
reset. When released from reset, the
transmit state machine immediately
transfers data from XRBUF[n] to XRSR[n].
The transmit state machine sets the
underrun flag (XUNDRN) in XSTAT, if
XRBUF[n] have not been preloaded with data
before reset is released. The transmit
state machine also immediately begins
detecting frame sync and is ready to
transmit. Transmit TDM time slot begins at
slot 0 after reset is released. |
| 10 | XSRCLR | R/W | 0h | Transmit serializer clear enable bit. By clearing then setting this bit, the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the next active time slot, an underrun will occur. 0 Transmit serializers are cleared.
1 Transmit serializers are active. When the
transmit serializers are first taken out of
reset (XSRCLR changes from 0 to 1), the
transmit data ready bit (XDATA) in XSTAT is
set to indicate XBUF is ready to be
written. |
| 9 | XHCLKRST | R/W | 0h | Transmit high-frequency clock divider reset enable bit. 0 Transmit high-frequency clock divider is
held in reset and passes through its input
as divide-by-1.
1 Transmit high-frequency clock divider is
running. |
| 8 | XCLKRST | R/W | 0h | Transmit clock divider reset enable bit. 0 Transmit clock divider is held in reset.
When the clock divider is in reset, it
passes through a divide-by-1 of its input.
1 Transmit clock divider is running. |
| 7:5 | RESERVED72 | R | 0h | |
| 4 | RFRST | R/W | 0h | Receive frame sync generator reset enable bit. 0 Receive frame sync generator is reset.
1 Receive frame sync generator is active.
When released from reset, the receive frame
sync generator begins counting serial
clocks and generating frame sync as
programmed. |
| 3 | RSMRST | R/W | 0h | Receive state machine reset enable bit. 0 Receive state machine is held in reset.
1 Receive state machine is released from
reset. When released from reset, the
receive state machine immediately begins
detecting frame sync and is ready to
receive. Receive TDM time slot begins at
slot 0 after reset is released. |
| 2 | RSRCLR | R/W | 0h | Receive serializer clear enable bit. By clearing then setting this bit, the receive buffer is flushed. 0 Receive serializers are cleared. 1 Receive serializers are active. |
| 1 | RHCLKRST | R/W | 0h | Receive high-frequency clock divider reset enable bit. 0 Receive high-frequency clock divider is
held in reset and passes through its input
as divide-by-1.
1 Receive high-frequency clock divider is
running. |
| 0 | RCLKRST | R/W | 0h | Receive high-frequency clock divider reset enable bit. 0 Receive clock divider is held in reset.
When the clock divider is in reset, it
passes through a divide-by-1 of its input.
1 Receive clock divider is running. |