SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin. The value after reset for register 4 depends on how the pins are being driven.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 0048h |
| MCASP1 | 02B1 0048h |
| MCASP2 | 02B2 0048h |
| MCASP3 | 02B3 0048h |
| MCASP4 | 02B4 0048h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED74 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED74 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED74 | XDMAERR | RDMAERR | XCKFAIL | RCKFAIL | XSYNCERR | ||
| R | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSYNCERR | XUNDRN | ROVRN | INSTAT | INEN | INPOL | MUTEN | |
| R/W | R/W | R/W | R | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED74 | R | 0h | |
| 12 | XDMAERR | R/W | 0h | If transmit DMA error [XDMAERR], drive AMUTE active enable bit. 0 Drive is disabled. Detection of transmit
DMA error is ignored by AMUTE.
1 Drive is enabled (active). Upon detection
of transmit DMA error, AMUTE is active and
is driven according to MUTEN bit. |
| 11 | RDMAERR | R/W | 0h | If receive DMA error [RDMAERR], drive AMUTE active enable bit. 0 Drive is disabled. Detection of receive DMA
error is ignored by AMUTE.
1 Drive is enabled (active). Upon detection
of receive DMA error, AMUTE is active and
is driven according to MUTEN bit. |
| 10 | XCKFAIL | R/W | 0h | If transmit clock failure [XCKFAIL], drive AMUTE active enable bit. 0 Drive is disabled. Detection of transmit
clock failure is ignored by AMUTE.
1 Drive is enabled (active). Upon detection
of transmit clock failure, AMUTE is active
and is driven according to MUTEN bit |
| 9 | RCKFAIL | R/W | 0h | If receive clock failure [RCKFAIL], drive AMUTE active enable bit. 0 Drive is disabled. Detection of receive
clock failure is ignored by AMUTE.
1 Drive is enabled (active). Upon detection
of receive clock failure, AMUTE is active
and is driven according to MUTEN bit. |
| 8 | XSYNCERR | R/W | 0h | If unexpected transmit frame sync error [XSYNCERR], drive AMUTE active enable bit. 0 Drive is disabled. Detection of unexpected
transmit frame sync error is ignored by
AMUTE.
1 Drive is enabled (active). Upon detection
of unexpected transmit frame sync error,
AMUTE is active and is driven according to
MUTEN bit. |
| 7 | RSYNCERR | R/W | 0h | If unexpected receive frame sync error [RSYNCERR], drive AMUTE active enable bit. 0 Drive is disabled. Detection of unexpected
receive frame sync error is ignored by
AMUTE.
1 Drive is enabled (active). Upon detection
of unexpected receive frame sync error,
AMUTE is active and is driven according to
MUTEN bit. |
| 6 | XUNDRN | R/W | 0h | If transmit underrun error [XUNDRN], drive AMUTE active enable bit. 0 Drive is disabled. Detection of transmit
underrun error is ignored by AMUTE.
1 Drive is enabled (active). Upon detection
of transmit underrun error, AMUTE is active
and is driven according to MUTEN bit. |
| 5 | ROVRN | R/W | 0h | If receiver overrun error [ROVRN], drive AMUTE active enable bit. 0 Drive is disabled. Detection of receiver
overrun error is ignored by AMUTE.
1 Drive is enabled (active). Upon detection
of receiver overrun error, AMUTE is active
and is driven according to MUTEN bit. |
| 4 | INSTAT | R | 0h | Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1. 0 AMUTEIN pin is inactive.
1 AMUTEIN pin is active. Audio mute in error
is detected. |
| 3 | INEN | R/W | 0h | Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]. 0 Drive is disabled. AMUTEIN is ignored by
AMUTE.
1 Drive is enabled (active). INSTAT = 1
drives AMUTE active. |
| 2 | INPOL | R/W | 0h | Audio mute in [AMUTEIN] polarity select bit. 0 Polarity is active high. A high on AMUTEIN
sets INSTAT to 1.
1 Polarity is active low. A low on AM UTEIN
sets INSTAT to 1. |
| 1:0 | MUTEN | R/W | 0h | AMUTE pin enable bit [unless overridden by GPIO registers]. 0 AMUTE pin is disabled, pin goes to tri-
state condition.
1 AMUTE pin is driven high if error is
detected.
2 AMUTE pin is driven low if error is
detected.
3 Reserved |