SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 004Ch |
| MCASP1 | 02B1 004Ch |
| MCASP2 | 02B2 004Ch |
| MCASP3 | 02B3 004Ch |
| MCASP4 | 02B4 004Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED75 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED75 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED75 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED75 | MODE | ORD | DLBEN | ||||
| R | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED75 | R | 0h | |
| 3:2 | MODE | R/W | 0h | Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]. 0 Default and reserved on loopback mode
(DLBEN = 1). When in non-loopback mode
(DLBEN = 0), MODE should be left at default
(00). When in loopback mode (DLBEN = 1),
MODE = 00 is reserved and is not
applicable.
1 Transmit clock and frame sync generators
used by both transmit and receive sections.
When in loopback mode (DLBEN = 1), MODE
must be 01.
2 Reserved.
3 Reserved. |
| 1 | ORD | R/W | 0h | Loopback order bit when loopback mode is enabled [DLBEN = 1]. 0 Odd serializers N + 1 transmit to even
serializers N that receive. The
corresponding serializers must be
programmed properly.
1 Even serializers N transmit to odd
serializers N + 1 that receive. The
corresponding serializers must be
programmed properly. |
| 0 | DLBEN | R/W | 0h | Loopback mode enable bit. 0 Loopback mode is disabled. 1 Loopback mode is enabled. |