SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL) affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL. RGBLCTL allows the receiver to be reset independently from the transmitter.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 0060h |
| MCASP1 | 02B1 0060h |
| MCASP2 | 02B2 0060h |
| MCASP3 | 02B3 0060h |
| MCASP4 | 02B4 0060h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED79 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED79 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED79 | XFRST | XSMRST | XSRCLR | XHCLKRST | XCLKRST | ||
| R | R | R | R | R | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED78 | RFRST | RSMRST | RSRCLR | RHCLKRST | RCLKRST | ||
| R | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED79 | R | 0h | |
| 12 | XFRST | R | 0h | Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of GBLCTL. Writes have no effect. |
| 11 | XSMRST | R | 0h | Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of GBLCTL. Writes have no effect. |
| 10 | XSRCLR | R | 0h | Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of GBLCTL. Writes have no effect. |
| 9 | XHCLKRST | R | 0h | Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of GBLCTL. Writes have no effect. |
| 8 | XCLKRST | R | 0h | Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of GBLCTL. Writes have no effect. |
| 7:5 | RESERVED78 | R | 0h | |
| 4 | RFRST | R/W | 0h | Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of GBLCTL. 0 Receive frame sync generator is reset. 1 Receive frame sync generator is active. |
| 3 | RSMRST | R/W | 0h | Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of GBLCTL. 0 Receive state machine is held in reset.
1 Receive state machine is released from
reset. |
| 2 | RSRCLR | R/W | 0h | Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of GBLCTL. 0 Receive serializers are cleared. 1 Receive serializers are active. |
| 1 | RHCLKRST | R/W | 0h | Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of GBLCTL. 0 Receive high-frequency clock divider is
held in reset and passes through its input
as divide-by-1.
1 Receive high-frequency clock divider is
running. |
| 0 | RCLKRST | R/W | 0h | Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL. 0 Receive clock divider is held in reset. 1 Receive clock divider is running. |