SPRUJC6 User guide

SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1

2.2.22.1 MCASP_RCLKCHK Register (Offset = 88h) [reset = 0h]

The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit.

Table 14-11131 Instance Table

Figure 14-5515 MCASP_RCLKCHK Name Register

Table 14-11132 MCASP_RCLKCHK Register Field Descriptions

Bit	Field	Type	Reset	Description
31:24	RCNT	R	0h	Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency controller clock [AHCLKR] signals, and stores the count in RCNT until the next measurement is taken.
23:16	RMAX	R/W	0h	Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency controller clock [AHCLKR] signals have been received. If the current counter value is greater than RMAX after counting 32 AHCLKR signals, RCKFAIL in RSTAT is set. The comparison is performed using unsigned arithmetic.
15:8	RMIN	R/W	0h	Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency controller clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32 AHCLKR signals, RCKFAIL in RSTAT is set. The comparison is performed using unsigned arithmetic.
7:4	RESERVED93	R	0h
3:0	RPS	R/W	0h	Receive clock check prescaler value. 0 McASP system clock divided by 1. 1 McASP system clock divided by 2. 2 McASP system clock divided by 4. 3 McASP system clock divided by 8. 4 McASP system clock divided by 16. 5 McASP system clock divided by 32. 6 McASP system clock divided by 64. 7 McASP system clock divided by 128. 8 McASP system clock divided by 256. 9 Reserved from 9h to Fh.