SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP condition(s) generates XINT. See the XSTAT register for a description of the interrupt conditions.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 00BCh |
| MCASP1 | 02B1 00BCh |
| MCASP2 | 02B2 00BCh |
| MCASP3 | 02B3 00BCh |
| MCASP4 | 02B4 00BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED106 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED106 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED106 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| XSTAFRM | RESERVED105 | XDATA | XLAST | XDMAERR | XCKFAIL | XSYNCERR | XUNDRN |
| R/W | R | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED106 | R | 0h | |
| 7 | XSTAFRM | R/W | 0h | Transmit start of frame interrupt enable bit. 0 Interrupt is disabled. A transmit start of
frame interrupt does not generate a McASP
transmit interrupt (XINT).
1 Interrupt is enabled. A transmit start of
frame interrupt generates a McASP transmit
interrupt (XINT). |
| 6 | RESERVED105 | R | 0h | |
| 5 | XDATA | R/W | 0h | Transmit data ready interrupt enable bit. 0 Interrupt is disabled. A transmit data
ready interrupt does not generate a McASP
transmit interrupt (XINT).
1 Interrupt is enabled. A transmit data ready
interrupt generates a McASP transmit
interrupt (XINT). |
| 4 | XLAST | R/W | 0h | Transmit last slot interrupt enable bit. 0 Interrupt is disabled. A transmit last slot
interrupt does not generate a McASP
transmit interrupt (XINT).
1 Interrupt is enabled. A transmit last slot
interrupt generates a McASP transmit
interrupt (XINT). |
| 3 | XDMAERR | R/W | 0h | Transmit DMA error interrupt enable bit. 0 Interrupt is disabled. A transmit DMA error
interrupt does not generate a McASP
transmit interrupt (XINT).
1 Interrupt is enabled. A transmit DMA error
interrupt generates a McASP transmit
interrupt (XINT). |
| 2 | XCKFAIL | R/W | 0h | Transmit clock failure interrupt enable bit. 0 Interrupt is disabled. A transmit clock
failure interrupt does not generate a McASP
transmit interrupt (XINT).
1 Interrupt is enabled. A transmit clock
failure interrupt generates a McASP
transmit interrupt (XINT). |
| 1 | XSYNCERR | R/W | 0h | Unexpected transmit frame sync interrupt enable bit. 0 Interrupt is disabled. An unexpected
transmit frame sync interrupt does not
generate a McASP transmit interrupt (XINT).
1 Interrupt is enabled. An unexpected
transmit frame sync interrupt generates a
McASP transmit interrupt (XINT). |
| 0 | XUNDRN | R/W | 0h | Transmitter underrun interrupt enable bit. 0 Interrupt is disabled. A transmitter
underrun interrupt does not generate a
McASP transmit interrupt (XINT).
1 Interrupt is enabled. A transmitter
underrun interrupt generates a McASP
transmit interrupt (XINT). |