SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
See reference [R1].
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| Instance Name | Physical Address |
|---|---|
| MLB0 | 02F8 2014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| MCS | |||||||
| R/W0TC | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| MCS | |||||||
| R/W0TC | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MCS | |||||||
| R/W0TC | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MCS | |||||||
| R/W0TC | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | MCS | R/W0TC | 0h | MediaLB channel status. Indicates the channel status for MediaLB channels 63 to 32. Channel status bits are set by hardware and cleared by software. Status is only set if the appropriate bits in the MIEN register are set. Reset Source: prst_n |