SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
See reference [R1].
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| Instance Name | Physical Address |
|---|---|
| MLB0 | 02F8 20E4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| WNR | TB | RSV0 | |||||
| R/W | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSV0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSV0 | ADDR1 | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | WNR | R/W | 0h | Write-Not-Read selection (0 = read, 1 = write) Reset Source: prst_n |
| 30 | TB | R/W | 0h | Target location bit (0 = selects CTR, 1 = selects DBR) Reset Source: prst_n |
| 29:14 | RSV0 | R/W | 0h | Reserved (write default value) Reset Source: prst_n |
| 13:8 | ADDR1 | R/W | 0h | DBR address of 8-bit entry - bits[13:8] Reset Source: prst_n |
| 7:0 | ADDR0 | R/W | 0h | CTR address of 128-bit entry or DBR address of 8-bit entry - bits[7:0] Reset Source: prst_n |