SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Clock management configuration
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| Instance Name | Physical Address |
|---|---|
| MCSPI0 | 2010 0010h |
| MCSPI1 | 2011 0010h |
| MCSPI2 | 2012 0010h |
| MCSPI3 | 2013 0010h |
| MCSPI4 | 2014 0010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | IDLEMODE | FREEEMU | SOFTRESET | ||||
| R | R/W | R/W | R/W | ||||
| 0h | 2h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RSVD | R | 0h | Reserved |
| 3:2 | IDLEMODE | R/W | 2h | Configuration of the local target state management mode By definition, target can handle read/write transaction as long as it is out of IDLE state 0 Force-idle mode: local target's IDLE state
follows (acknowledges) the system's clock
stop requests unconditionally, that is,
regardless of the IP module's internal
requirements. Backup mode, for debug only.
1 No-idle mode: local target never enters
IDLE state. Backup mode, for debug only.
2 Smart-idle mode: local target's IDLE state
eventually follows (acknowledges) the
system's clock stop requests, depending on
the IP module's internal requirements. IP
module shall not generate (IRQ- or DMA-
request-related) wake-up events.
3 Smart-idle wake-up-capable mode: local
target's IDLE state eventually follows
(acknowledges) the system's clock stop
requests, depending on the IP module's
internal requirements. IP module may
generate (IRQ- or DMA-request-related)
wake-up events when in IDLE state. |
| 1 | FREEEMU | R/W | 0h | Sensitivity to emulation [debug] suspend input signal 0 IP module is sensitive to emulation
suspend.
1 IP module is not sensitive to emulation
suspend. |
| 0 | SOFTRESET | R/W | 0h | Software reset [Optional] 0 Reset done, no pending action 1 Initiate software reset |