SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Enhanced Features Register 2
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 008Ch |
| UART1 | 0281 008Ch |
| UART2 | 0282 008Ch |
| UART3 | 0283 008Ch |
| UART4 | 0284 008Ch |
| UART5 | 0285 008Ch |
| UART6 | 0286 008Ch |
| WKUP_UART0 | 2B30 008Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BROADCAST | TIMEOUT_BEHAVE | C8 | C4 | C2 | MULTIDROP | RHR_OVERRUN | ENDIAN |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED1 | R | 0h | |
| 7 | BROADCAST | R/W | 0h | Enables broadcast address matching in multi-drop address match mode Reset Source: mod_g_arstn |
| 6 | TIMEOUT_BEHAVE | R/W | 0h | Specifies how timeout is measured 0 timeout after at least one character has
been received
1 periodic timeout even when no character has
been received |
| 5 | C8 | R/W | 0h | Value for ISO 7816 C8 pin for software control Reset Source: mod_g_arstn |
| 4 | C4 | R/W | 0h | Value for ISO 7816 C4 pin for software control Reset Source: mod_g_arstn |
| 3 | C2 | R/W | 0h | Value for ISO 7816 reset pin [software controllable] Reset Source: mod_g_arstn |
| 2 | MULTIDROP | R/W | 0h | Enables parity Multi-drop mode [overrides LCR[5..3]] when '1' Reset Source: mod_g_arstn |
| 1 | RHR_OVERRUN | R/W | 0h | RHR Overrun behaviour when buffer full 0 data in RHR is not overwritten (standard)
1 data in RHR is overwritten when buffer full
(and FIFO disabled) |
| 0 | ENDIAN | R/W | 0h | Endianness 0 Little Endian (LSB First) 1 Big Endian (MSB First) |