SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Register containing PLL bypass select, BIST control and status
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 000Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED31_18 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED31_18 | BIST_MODE | BIST_ERROR_COUNT | |||||
| R | R/W | R | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| BIST_ERROR_COUNT | BIST_ERROR | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BIST_COMPLETE | BIST_ON | BIST_MODE_EN | BIST_MODE_SEL | RESERVED0 | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:18 | RESERVED31_18 | R | 0h | Reserved bits |
| 17 | BIST_MODE | R/W | 0h | Set for bist mode. This is used for overriding PHY ports for BIST. Reset Source: cfg_srst_n |
| 16:9 | BIST_ERROR_COUNT | R | 0h | Number of bytes that have errors while running BIST. The count resets when bist_on is set. Reset Source: cfg_srst_n |
| 8 | BIST_ERROR | R | 0h | If set, this bit indicates that BIST completed with error. Reset Source: cfg_srst_n |
| 7 | BIST_COMPLETE | R | 0h | If set, this bit indicates that the BIST operation is completed. Reset Source: cfg_srst_n |
| 6 | BIST_ON | R/W | 0h | Setting this bit starts the BIST operation. Reset Source: cfg_srst_n |
| 5 | BIST_MODE_EN | R/W | 0h | BIST Mode Enable. 0 = BIST not enabled, 1 = BIST enabled Reset Source: cfg_srst_n |
| 4:1 | BIST_MODE_SEL | R/W | 0h | BIST Mode Selection. bist_mode_sel[3]: 0 = 8-bit interface, 1 = 16-bit interface; bist_mode_sel[2]: 0 = error injection disabled, 1 = error injection enabled; bist_mode_sel[1]: 0 = device mode, 1 = host mode; bist_mode_sel[0]: 0 = High Speed mode, 1 = Full Speed mode. Reset Source: cfg_srst_n |
| 0 | RESERVED0 | R/W | 0h | Reserved bits |