SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
BG bias current trimming
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 8088h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BG_ANA_REG2 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7:0 | BG_ANA_REG2 | R/W | 0h | Bits 7:5= 000 High speed receiver bias 5uA, 100 High speed receiver bias 1uA, 001 High speed receiver bias 4uA, 010 High speed receiver bias 6uA, 101 High speed receiver bias 2uA. Bits 4:2= 000 Trasmission Envelope Detector bias current 5uA, 100 Trasmission Envelope Detector bias current 1uA, 001 Trasmission Envelope Detector bias current 4uA, 101 Trasmission Envelope Detector bias current 6uA, 101 Trasmission Envelope Detector bias current 2uA. Bits 1:0=00 PLL LDO bias current 5uA, 01 PLL LDO bias current 6uA, 10 PLL LDO bias current 4uA, 11 PLL LDO bias current 5uA Reset Source: usb2_sync_preset_n |