SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Capability Parameters 1 Register For register definitions, refer to the xHCI specification.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 0010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| XECP | |||||||
| R | |||||||
| 258h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| XECP | |||||||
| R | |||||||
| 258h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MAXPSASIZE | CFC | SEC | SPC | PAE | |||
| R | R | R | R | R | |||
| Fh | 1h | 1h | 1h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NSS | LTC | LHRC | PIND | PPC | CSZ | BNC | AC64 |
| R | R | R | R | R | R | R | R |
| 0h | 1h | 1h | 0h | 1h | 1h | 0h | 1h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | XECP | R | 258h | xHCI Extended Capabilities Pointer [xECP] Based on configuration, controller automatically updates it. Refer to <workspace>/src/DWC_usb3_params.v for details on DWC_USB3_HC_XECP. Reset Source: rst_mod_g_rst_n |
| 15:12 | MAXPSASIZE | R | Fh | Maximum Primary Stream Array Size [MaxPSASize] For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 11 | CFC | R | 1h | Contiguous Frame ID Capability [CFC] Reset Source: rst_mod_g_rst_n |
| 10 | SEC | R | 1h | Stopped EDLTA Capability [SEC] For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 9 | SPC | R | 1h | Short Packet Capability [SPC] For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 8 | PAE | R | 0h | Parse All Event Data [PAE] For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 7 | NSS | R | 0h | No Secondary SID Support [NSS] For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 6 | LTC | R | 1h | Latency Tolerance Messaging Capability [LTC] For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 5 | LHRC | R | 1h | Light HC Reset Capability For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 4 | PIND | R | 0h | Port Indicators [PIND] For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 3 | PPC | R | 1h | Port Power Control For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 2 | CSZ | R | 1h | Context Size [CSZ] For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 1 | BNC | R | 0h | BW Negotiation Capability [BNC] For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 0 | AC64 | R | 1h | 64-bit Addressing Capability [AC64] For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |