SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global Debug LSP MUX Register - Host This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration, then the default values readout is X (Undefined). Bit Bash test should not be done on this debug register.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C170h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| LOGIC_ANALYZER_TRACE | |||||||
| R/W | |||||||
| 3Fh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_15_14 | HOSTSELECT | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HOSTSELECT | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | RESERVED_31_24 | R | 0h | Reserved |
| 23:16 | LOGIC_ANALYZER_TRACE | R/W | 3Fh | logic_analyzer_trace Port MUX Select Currently only bits[21:16] are used. For details on how the mux controls the debug traces, refer to the "assign logic_analyzer_trace =" code section in the DWC_usb3.v file. A value of 6'h3F drives 0s on the logic_analyzer_trace signal. If you plan to OR [instead using a mux] this signal with other trace signals in your system to generate a common trace signal, you can use this feature. Reset Source: rst_mod_g_rst_n |
| 15:14 | RESERVED_15_14 | R | 0h | Reserved |
| 13:0 | HOSTSELECT | R/W | 0h | Device LSP Select Selects the LSP debug information presented in the GDBGLSP register in host mode. Reset Source: rst_mod_g_rst_n |