SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global User Control Register 2: This register provides a few options for the software to control the controller behavior in the Host and device mode. Most of the options are used to improve inter-operability with different hosts and devices.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C19Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_26 | EN_HP_PM_TIMER | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| EN_HP_PM_TIMER | NOLOWPWRDUR | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| NOLOWPWRDUR | RST_ACTBITLATER | RESERVED_13 | ENABLEEPCACHEEVICT | DISABLECFC | RXPINGDURATION | ||
| R/W | R/W | R | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RXPINGDURATION | TXPINGDURATION | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED_31_26 | R/W | 0h | Reserved |
| 25:19 | EN_HP_PM_TIMER | R/W | 0h | This register field is used to set new HP and PM timers. - To enable PM timer, set GUCTL2[19] bit as 1. - To enable HP timer, set GUCTL2[20] bit as 1. Default value of HP timer is 4us when HP PM timer is not enabled. when new HP timer is enabled default value is 12us. Use GUCTL2[25:21] to specify HP timer value in microseconds. Reset Source: rst_mod_g_rst_n |
| 18:15 | NOLOWPWRDUR | R/W | 0h | No Low Power Duration [NOLOWPWRDUR] This bit is applicable for device mode only and is ignored in host mode. After starting a transfer on a SS ISOC endpoint, the application must program these bits to prevent the device to lose frame synchronization over a period of time. Based on this count-down counter, the device will wake itself from U1/U2 low power states. After entering to U0 state and receiving two ITPs [which will sync-up the host and the device], U1/U2 low power entry is allowed. Each count represents the duration in terms of milliseconds. For example, a value of 3 represents 3ms. Note: - To disable this feature, set this field to 4'b0. - These bits are applicable only in device mode and ignored in host mode. - Some xHCI hosts do not send ITPs when performing ISOC transfers when the link enters U1/U2 low power states. This causes the device to lose frame synchronization over a period of time resulting in ISOC packets being dropped. Reset Source: rst_mod_g_rst_n |
| 14 | RST_ACTBITLATER | R/W | 0h | Enable clearing of the command active bit for the ENDXFER command after the command execution is completed. This bit is valid in device mode only. Reset Source: rst_mod_g_rst_n |
| 13 | RESERVED_13 | R | 0h | Reserved for future use |
| 12 | ENABLEEPCACHEEVICT | R/W | 0h | Enable Evicting Endpoint cache after Flow Control for bulk endpoints. In 3.00a release, a performance enhancement was done to keep the non-stream capable bulk IN endpoint in cache after flow control. Setting this bit will disable this enhancement. This should be set only for debug purpose. Reset Source: rst_mod_g_rst_n |
| 11 | DISABLECFC | R/W | 0h | Disable xHCI Errata Feature Contiguous Frame ID Capability This field controls the xHCI Errata feature Contiguous FrameID capability. When set, the xHCI HCCPARAMS1 bit 11 will be set to 0 indicating that CFC is not supported. Disable this feature only if your application cannot tolerate Misssed Service Error events for Isoc transfers, and your system latencies are large to cause Missed Service errors even if the software is following the Isochronous Thresholding rules. Reset Source: rst_mod_g_rst_n |
| 10:5 | RXPINGDURATION | R/W | 0h | Recieve Ping Maximum Duration This field is relevant to Host mode and controls the maximum duration of received LFPS to be treated as a Ping LFPS. The Max duration of the Ping LFPS is controlled by programming this value and is in terms of 8 ns granularity. Eg: A value of 32 indicates 256 ns. Reset Source: rst_mod_g_rst_n |
| 4:0 | TXPINGDURATION | R/W | 0h | Transmit Ping Maximum Duration This field is relevant to Device mode and controls the maximum duration for which the controller should instruct the PHY to transmit a Ping LFPS. The duration of the Ping LFPS is controlled by programming this value and is in terms of 8 ns granularity. Eg: A value of 13 indicates 104 ns. Reset Source: rst_mod_g_rst_n |