SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global User Control Register 3 This register provides a few options for the software to control the controller behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C60Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_17 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_31_17 | SCH_PING_EARLY | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_15_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_15_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:17 | RESERVED_31_17 | R/W | 0h | Reserved |
| 16 | SCH_PING_EARLY | R/W | 0h | Enable SuperSpeed Ping Transaction Packet scheduling early in the microframe. This bit is valid in Host mode only. Reset Source: rst_mod_g_rst_n |
| 15:0 | RESERVED_15_0 | R/W | 0h | Reserved |