SPRUJC6 User guide

SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1

14.7.3.2.2.383 USB2SS_LINK_LINK_LLUCTL Register

2.2.383.1 USB2SS_LINK_LINK_LLUCTL Register (Offset = 24h) [reset = 800080h]

Link User Control Register - Link Layer User Control Register for enabling Link/PHY-specific options. - This register is common for all SS ports.

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Table 14-13401 Instance Table

Instance Name	Physical Address
USB0	3100 D024h + formula

Figure 14-6633 USB2SS_LINK_LINK_LLUCTL Name Register

31	30	29	28	27	26	25	24
RESERVED_30_31		SUPPORT_P4_PG	SUPPORT_P4	RESERVED_24_27
R/W		R/W	R/W	R/W
0h		0h	0h	0h
23	22	21	20	19	18	17	16
DISRXDET_LTSSM_TIMER_OVRRD	RESERVED_13_22
R/W	R/W
1h	0h
15	14	13	12	11	10	9	8
RESERVED_13_22			U2P3CPMOK	EN_RESET_PIPE_AFTER_PHY_MUX	RESERVED_8_10
R/W			R/W	R/W	R/W
0h			0h	0h	0h
7	6	5	4	3	2	1	0
MASK_PIPE_RESET	RESERVED_6	NO_UX_EXIT_P0_TRANS	RESERVED_0_4
R/W	R/W	R/W	R/W
1h	0h	0h	0h

Table 14-13402 USB2SS_LINK_LINK_LLUCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RESERVED_30_31	R/W	0h	Reserved
29	SUPPORT_P4_PG	R/W	0h	PHY P4 Power gate mode [PG] is enabled. Set this bit if the PHY supports PG mode in P4. This bit is used only for Synopsys PHY. Reset Source: rst_mod_g_rst_n
28	SUPPORT_P4	R/W	0h	Support PHY P3.CPM and P4 Power States. When this bit is set, the controller puts the PHY in P3.CPM or P4 in certain states. This bit is used only for Synopsys PHY. Reset Source: rst_mod_g_rst_n
27:24	RESERVED_24_27	R/W	0h	Reserved
23	DISRXDET_LTSSM_TIMER_OVRRD	R/W	1h	DisRxDet_LTSSM_Timer_Ovrrd. When DisRxDetU3RxDet is asserted in Polling or U1, the timeout expires immediately. Reset Source: rst_mod_g_rst_n
22:13	RESERVED_13_22	R/W	0h	Reserved
12	U2P3CPMOK	R/W	0h	P3CPM OK for U2/SSInactive [U2P3CPMok] - 0: During link state U2/SS.Inactive, put PHY in P2 [Default] - 1: During link state U2/SS.Inactive, put PHY in P3CPM. Note: For a port, if both GUCTL1[25]=1 and LUCTL[12]=1, LUCTL[12]=1 takes priority. Reset Source: rst_mod_g_rst_n
11	EN_RESET_PIPE_AFTER_PHY_MUX	R/W	0h	en_reset_pipe_after_phy_mux. The controller issues USB 3.0 PHY reset after DisRxDetU3RxDet is de-asserted. Reset Source: rst_mod_g_rst_n
10:8	RESERVED_8_10	R/W	0h	Reserved
7	MASK_PIPE_RESET	R/W	1h	Mask pipe reset. If this bit is set, controller blocks pipe_reset_n from going to the PHY when DisRxDetU3RxDet=1. Reset Source: rst_mod_g_rst_n
6	RESERVED_6	R/W	0h	Reserved
5	NO_UX_EXIT_P0_TRANS	R/W	0h	no_ux_exit_p0_trans. Link LTSSM detects Ux_exit LFPS when P0 transition is on-going by default. If this bit is set, Link LTSSM may miss Ux_exit LFPS when P0 transition is happening. Reset Source: rst_mod_g_rst_n
4:0	RESERVED_0_4	R/W	0h	Reserved