SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| PSC | Power Domain | LPSC Name | LPSC Index | Default State | Software | Modules |
|---|---|---|---|---|---|---|
| WKUP_PSC0 | GP_CORE_CTL_MCU | LPSC_MCU_ALWAYSON | 0 | ON | NO | MCU_CTRL_MMR0 |
| WKUP_PSC0 | GP_CORE_CTL_MCU | MCU_MCU_GPIO_INTROUTER0 | ||||
| WKUP_PSC0 | GP_CORE_CTL_MCU | MCU_PADCFG_CTRL0 | ||||
| WKUP_PSC0 | GP_CORE_CTL_MCU | WKUP_PLL0 | ||||
| WKUP_PSC0 | GP_CORE_CTL_MCU | MCU_DCC0 | ||||
| WKUP_PSC0 | GP_CORE_CTL_MCU | MCU_DCC1 | ||||
| WKUP_PSC0 | GP_CORE_CTL_MCU | WKUP_ESM0 | ||||
| WKUP_PSC0 | GP_CORE_CTL_MCU | MCU_GPIO0 | ||||
| WKUP_PSC0 | GP_CORE_CTL_MCU | LPSC_DM2SAFE_ISO | 3 | ON | YES | |
| WKUP_PSC0 | GP_CORE_CTL_MCU | LPSC_MCU_TEST | 5 | ON | YES | |
| WKUP_PSC0 | PD_MCUSS | LPSC_MCU_COMMON | 9 | ON | YES | WKUP_PSRAM2KX32E0 |
| WKUP_PSC0 | PD_MCUSS | LPSC_MCU_PBIST | 10 | OFF | YES | WKUP_PBIST1 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MAIN_CTRL_MMR0 |
| MAIN_PSC0 | GP_CORE | MAIN_GPIO_INTROUTER0 | ||||
| MAIN_PSC0 | GP_CORE | PADCFG_CTRL0 | ||||
| MAIN_PSC0 | GP_CORE | PLL0 | ||||
| MAIN_PSC0 | GP_CORE | TIMESYNC_INTROUTER0 | ||||
| MAIN_PSC0 | GP_CORE | WKUP_CTRL_MMR0 | ||||
| MAIN_PSC0 | GP_CORE | WKUP_WKUP_SEC_MMR0 | ||||
| MAIN_PSC0 | GP_CORE | CPT2_AGGR1 | ||||
| MAIN_PSC0 | GP_CORE | DCC0 | ||||
| MAIN_PSC0 | GP_CORE | DCC1 | ||||
| MAIN_PSC0 | GP_CORE | DCC2 | ||||
| MAIN_PSC0 | GP_CORE | DCC3 | ||||
| MAIN_PSC0 | GP_CORE | DCC4 | ||||
| MAIN_PSC0 | GP_CORE | DCC5 | ||||
| MAIN_PSC0 | GP_CORE | DCC6 | ||||
| MAIN_PSC0 | GP_CORE | DCC7 | ||||
| MAIN_PSC0 | GP_CORE | DCC8 | ||||
| MAIN_PSC0 | GP_CORE | WKUP_TIMER0 | ||||
| MAIN_PSC0 | GP_CORE | WKUP_TIMER1 | ||||
| MAIN_PSC0 | GP_CORE | ESM0 | ||||
| MAIN_PSC0 | GP_CORE | GPIO0 | ||||
| MAIN_PSC0 | GP_CORE | GPIO1 | ||||
| MAIN_PSC0 | GP_CORE | WKUP_GTC0 | ||||
| MAIN_PSC0 | GP_CORE | DDPA0 | ||||
| MAIN_PSC0 | GP_CORE | WKUP_VTM0 | ||||
| MAIN_PSC0 | GP_CORE | WKUP_I2C0 | ||||
| MAIN_PSC0 | GP_CORE | PSRAMECC0 | ||||
| MAIN_PSC0 | GP_CORE | WKUP_PSRAMECC_8K0 | ||||
| MAIN_PSC0 | GP_CORE | WKUP_ROM0 | ||||
| MAIN_PSC0 | GP_CORE | WKUP_RTCSS0 | ||||
| MAIN_PSC0 | GP_CORE | EFUSE0 | ||||
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_DM | 1 | OFF | YES | WKUP_R5FSS0 |
| MAIN_PSC0 | GP_CORE | WKUP_RTI0 | ||||
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_DM_PBIST0 | 2 | ON | YES | WKUP_PBIST0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MAIN2DM_ISO | 3 | ON | YES | |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_DM2MAIN_ISO | 4 | ON | YES | |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_DM2MAIN_INFRA_ISO | 5 | ON | YES | |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_DM2CENTRAL_ISO | 6 | ON | YES | |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_CENTRAL2DM_ISO | 7 | ON | YES | |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_DM_PBIST1 | 8 | ON | YES | |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_TEST | 9 | ON | YES | DFTSS0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_DEBUGSS | 10 | ON | YES | DBG_INTROUTER0 |
| MAIN_PSC0 | GP_CORE | STM0 | ||||
| MAIN_PSC0 | GP_CORE | DEBUGSS_WRAP0 | ||||
| MAIN_PSC0 | GP_CORE | DEBUGSS0 | ||||
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_PBIST0 | 11 | OFF | YES | PBIST0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_USB0 | 12 | OFF | YES | USB0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_USB0_ISO | 13 | OFF | YES | |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | PDMA_AASRC0_6 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | PDMA_AASRC1_7 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | PDMA5 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | PDMA3 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | CPT2_AGGR0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | CPT2_AGGR2 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER1 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER10 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER11 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER12 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER13 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER14 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER15 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER2 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER3 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER4 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER5 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER6 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER7 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER8 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | TIMER9 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | ECAP0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | ECAP1 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | ECAP2 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | ECAP3 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | ECAP4 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | ECAP5 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | EPWM0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | EPWM1 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | EPWM2 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | MCRC64_0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | I2C0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | I2C1 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | I2C2 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | I2C3 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | I2C4 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | I2C5 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | I2C6 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | PDMA2 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | MCSPI0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | MCSPI1 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | MCSPI2 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | MCSPI3 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | MCSPI4 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | UART0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | UART1 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | UART2 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | UART3 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | UART4 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | UART5 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | UART6 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | WKUP_UART0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP1_RSVD | 19 | OFF | YES | PDMA4 |
| MAIN_PSC0 | GP_CORE | DMASS0 | ||||
| MAIN_PSC0 | GP_CORE | PDMA1 | ||||
| MAIN_PSC0 | GP_CORE | PDMA0 | ||||
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_EMMC8B | 20 | OFF | YES | MMCSD0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_CPSW | 21 | OFF | YES | CPSW0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_OSPI2_RSVD | 22 | OFF | YES | |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MCAN0 | 23 | OFF | YES | MCAN0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MCAN1 | 24 | OFF | YES | MCAN1 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MCAN2 | 25 | OFF | YES | MCAN2 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MCAN3 | 26 | OFF | YES | MCAN3 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MCAN4 | 27 | OFF | YES | MCAN4 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_OSPI0 | 28 | ON | YES | FSS_OF_UL0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_OPSI1 | 29 | ON | YES | FSS0_FSAS_0 |
| MAIN_PSC0 | GP_CORE | FSS0_HYPERBUS1P0_0 | ||||
| MAIN_PSC0 | GP_CORE | FSS0_OSPI_0 | ||||
| MAIN_PSC0 | GP_CORE | FSS0_OSPI_1 | ||||
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_HYPERBUS | 30 | ON | YES | FSS0_HYPERBUS1P0_0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_SA3UL | 31 | ON | YES | SA3_SS0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MCASP0 | 32 | OFF | YES | MCASP0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MCASP1 | 33 | OFF | YES | MCASP1 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MCASP2 | 34 | OFF | YES | MCASP2 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MCASP3 | 35 | OFF | YES | MCASP3 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MCASP4 | 36 | OFF | YES | MCASP4 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_ATL | 37 | OFF | YES | ATL0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_ASRC0 | 38 | OFF | YES | AASRC0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_ASRC1 | 39 | OFF | YES | AASRC1 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_MLB | 40 | OFF | YES | MLB0 |
| MAIN_PSC0 | GP_CORE | LPSC_MAIN_ADC | 41 | OFF | YES | ADC12FC_16FFC0 |
| MAIN_PSC0 | MAIN_SRAM0 | LPSC_MAIN_SRAM_0_1 | 43 | ON | YES | MSRAM_1MB0 |
| MAIN_PSC0 | MAIN_SRAM0 | MSRAM_1MB1 | ||||
| MAIN_PSC0 | MAIN_SRAM0 | LPSC_MAIN_SRAM_PBIST0 | 44 | OFF | YES | PBIST3 |
| MAIN_PSC0 | MAIN_SRAM0 | LPSC_MAIN_SRAM_PBIST1 | 45 | OFF | YES | PBIST4 |
| MAIN_PSC0 | MAIN_SRAM1 | LPSC_MAIN_SRAM_2_3 | 46 | ON | YES | MSRAM_1MB2 |
| MAIN_PSC0 | MAIN_SRAM1 | MSRAM_1MB3 | ||||
| MAIN_PSC0 | MAIN_SRAM1 | LPSC_MAIN_SRAM_PBIST2 | 47 | OFF | YES | PBIST5 |
| MAIN_PSC0 | MAIN_SRAM1 | LPSC_MAIN_SRAM_PBIST3 | 48 | OFF | YES | PBIST6 |
| MAIN_PSC0 | MAIN_SRAM2 | LPSC_MAIN_SRAM_4_5 | 49 | ON | YES | MSRAM_1MB4 |
| MAIN_PSC0 | MAIN_SRAM2 | MSRAM_1MB5 | ||||
| MAIN_PSC0 | MAIN_SRAM2 | LPSC_MAIN_SRAM_PBIST4 | 50 | OFF | YES | PBIST7 |
| MAIN_PSC0 | MAIN_SRAM2 | LPSC_MAIN_SRAM_PBIST5 | 51 | OFF | YES | PBIST8 |
| MAIN_PSC0 | R5SS_0 | LPSC_MAIN_R5SS0_CORE0 | 52 | OFF | YES | R5FSS0_CORE0 |
| MAIN_PSC0 | R5SS_0 | RL2_OF_CBA4_0 | ||||
| MAIN_PSC0 | R5SS_0 | RTI0 | ||||
| MAIN_PSC0 | R5SS_0 | LPSC_MAIN_R5SS0_CORE1 | 53 | OFF | YES | R5FSS0_CORE1 |
| MAIN_PSC0 | R5SS_0 | RL2_OF_CBA4_1 | ||||
| MAIN_PSC0 | R5SS_0 | RTI1 | ||||
| MAIN_PSC0 | R5SS_0 | LPSC_MAIN_R5SS0_PBIST | 54 | OFF | YES | PBIST1 |
| MAIN_PSC0 | R5SS_1 | LPSC_MAIN_R5SS1_CORE0 | 55 | OFF | YES | R5FSS1_CORE0 |
| MAIN_PSC0 | R5SS_1 | RL2_OF_CBA4_2 | ||||
| MAIN_PSC0 | R5SS_1 | RTI2 | ||||
| MAIN_PSC0 | R5SS_1 | LPSC_MAIN_R5SS1_CORE1 | 56 | OFF | YES | R5FSS1_CORE1 |
| MAIN_PSC0 | R5SS_1 | RL2_OF_CBA4_3 | ||||
| MAIN_PSC0 | R5SS_1 | RTI3 | ||||
| MAIN_PSC0 | R5SS_1 | LPSC_MAIN_R5SS1_PBIST | 57 | OFF | YES | PBIST2 |
| MAIN_PSC0 | C7X0 | LPSC_MAIN_C7X0_COMMON | 58 | OFF | YES | C7X256V0_CORE0 |
| MAIN_PSC0 | C7X0 | LPSC_MAIN_C7X0_CORE | 59 | OFF | YES | C7X256V_0_0_C7XV_CORE_0 |
| MAIN_PSC0 | C7X0 | RTI4 | ||||
| MAIN_PSC0 | C7X0 | LPSC_MAIN_C7X0_PBIST | 60 | OFF | YES | C7X256V0_PBIST |
| MAIN_PSC0 | C7X1 | LPSC_MAIN_C7X1_COMMON | 61 | OFF | YES | C7X256V1_CORE0 |
| MAIN_PSC0 | C7X1 | LPSC_MAIN_C7X1_CORE | 62 | OFF | YES | C7X256V_1_1_C7XV_CORE_0 |
| MAIN_PSC0 | C7X1 | RTI5 | ||||
| MAIN_PSC0 | C7X1 | LPSC_MAIN_C7X1_PBIST | 63 | OFF | YES | C7X256V1_PBIST |