SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
UHS-II Device Select Register
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 00BEh |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| INT_MSG_ENA | RESERVED | DEV_SEL | |||||
| R/W | NONE | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | INT_MSG_ENA | R/W | 0h | This bit enables receipt of INT MSG. If this bit is set to 1,receipt of INT MSG is informed by Card Interrupt in the Nor-mal Interrupt Status register. If this bit is set to 0, Host Con-troller ignores receipt of INT MSG and may not set the UHS-II Device Interrupt Code register. Support of INT MSG Interrupt is optional. If trying to set this bit to 1 but still this bit is read 0, INT MSG Interrupt is not sup-ported by the Host Controller. In this case, UHS-II Device Interrupt Status register always shall be read 0 and UHS-II Device Interrupt Code register may not be implemented. '0' Disabled '1' Enabled Reset Source: vbus_amod_g_rst_n |
| 6:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | DEV_SEL | R/W | 0h | Host Controller holds an INT MSG packet per device. One of INT MSGs [up to 15] can be selected by this field and read from the UHS-II Device Interrupt Code Register [0BFh]. This field is effective when INT MSG Enable is set to 1. The number of devices implemented in the Host Controller is indicated by Number of Devices supported in the UHS-II General Capabilities register. 0h Unselected [Default] 1h INT MSG of Device ID 1 is selected 2h INT MSG of Device ID 2 is selected ..... ..... Fh INT MSG of Device ID 15 is selected Reset Source: vbus_amod_g_rst_n |