SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Selects the clock divider of the USART4 functional clock
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 A250h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | USART4_CLK_CTRL_CLK_DIV_LD_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | USART4_CLK_CTRL_CLK_DIV_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 3h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:17 | RESERVED | NONE | 0h | Reserved |
| 16 | USART4_CLK_CTRL_CLK_DIV_LD_PROXY | R/W | 0h | Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART4 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed. Field values (others are reserved): 1'b0 - READY 1'b1 - LOAD Reset Source: mod_g_rst_n |
| 15:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | USART4_CLK_CTRL_CLK_DIV_PROXY | R/W | 3h | Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1 2'b01 - Divide by 2 2'b10 - Divide by 3 2'b11 - Divide by 4 Reset Source: mod_g_rst_n |