SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Memory configuration register for CS#
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| FSS1_HYPERBUS1P0_0 | 0FC3 4020h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| MAXEN | RFU8 | MAXLEN | |||||
| R/W | R | R/W | |||||
| 0h | 0h | 0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| MAXLEN | TCMO | ACS | |||||
| R/W | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RFU7 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RFU7 | CRT | DEVTYPE | RFU6 | WRAPSIZE | |||
| R | R/W | R/W | R | R/W | |||
| 0h | 0h | 0h | 0h | 3h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | MAXEN | R/W | 0h | Maximum length Enable 0: No configurable CS# low time 1: Configurable CS# low time When this bit 1, CS# low time can be configurable by MAXLEN bit. Reset Source: mod_g_rst_n |
| 30:27 | RFU8 | R | 0h | This field is reserved for future use Reset Source: mod_g_rst_n |
| 26:18 | MAXLEN | R/W | 0h | Maximum Length,This bit indicates maximum read/write transaction length to memory. This bit is ignored when MAXEN bit is 0. 000000000: 2 Byte [1 HyperBus CK] 000000001: 4 Byte [2 HyperBus CK] 000000010: 6 Byte [3 HyperBus CK] 111111111: 1024 Byte [512 HyperBus CK] Reset Source: mod_g_rst_n |
| 17 | TCMO | R/W | 0h | True Continuous Merge Option. 0 : No merging WRAP and INCR. 1 : Merging WRAP and INCR. Note that this function can be used with the HyperFlash with specific function. Please confirm whether it is corresponding HyperFlash before enabling this function. When HyperBus memory doesnt accept the 8-bit boundary address, and a wrapping burst access with ARSIZE=0 and ARADDR0=1 is used, this bit must not be set to 1. Reset Source: mod_g_rst_n |
| 16 | ACS | R/W | 0h | Asymmetry Cache Support. 0 : No asymmetry cache system support. 1 : Asymmetry cache system support. This function should be disabled if the HyperBus memory itself supports the asymmetry cache system. Reset Source: mod_g_rst_n |
| 15:6 | RFU7 | R | 0h | This field is reserved for future use Reset Source: mod_g_rst_n |
| 5 | CRT | R/W | 0h | Configuration Register Target. 0: Memory space 1: CR space . This bit indicates whether the read or write operation accesses the memory or CR space. This bit is mapped to CA-46 bit in HyperRAM. When using HyperFlash, Reset Source: mod_g_rst_n |
| 4 | DEVTYPE | R/W | 0h | Device Type. 0: HyperFlash,1: HyperRAM. Device type for control target Reset Source: mod_g_rst_n |
| 3:2 | RFU6 | R | 0h | This field is reserved for future use Reset Source: mod_g_rst_n |
| 1:0 | WRAPSIZE | R/W | 3h | Wrap Size.The wrap burst length of HyperBus memory. This bit is ignored when the asymmetry cache support bit is 0. When the asymmetry cache support is 1, this bit should be set the same as wrap size of configuration register in HyperBus memory. 00 :Reserved. 01 :64 Bytes. 10 :16 Bytes. 11 :32 Bytes. Reset Source: mod_g_rst_n |