SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| Field | Value | Description |
|---|---|---|
| SFDP | 0 | SFDP disabled |
| 1 | SFDP enabled | |
| Read cmd | 0 | 0x0B Read Command |
| 1 | 0xEE Read Command | |
| Mode | 0 | 1S-1S-1S mode @ 50MHz |
| 1 | 8D-8D-8D mode @ 25MHz |
xSPI Boot Pin Usage summarizes the OSPI pin configuration done by ROM code for xSPI boot device on port 0.
| Device Pin | Module Signal | Pull Enable | Pull Direction | Driver Index | Rx En/Dis | Pinmux Sel | Pad Configuration Register |
|---|---|---|---|---|---|---|---|
| OSPI0_CLK | OSPI0_CLK | Disable | NA | 0 | Disable | 0 | PADCONFIG0 |
| OSPI0_DQS | OSPI0_DQS | Disable | NA | 0 | Enable | 0 | PADCONFIG2 |
| OSPI0_D0 | OSPI0_D0 | Disable | NA | 0 | Enable | 0 | PADCONFIG3 |
| OSPI0_D1 | OSPI0_D1 | Disable | NA | 0 | Enable | 0 | PADCONFIG4 |
| OSPI0_D2 | OSPI0_D2 | Disable | NA | 0 | Enable | 0 | PADCONFIG5 |
| OSPI0_D3 | OSPI0_D3 | Disable | NA | 0 | Enable | 0 | PADCONFIG6 |
| OSPI0_D4 | OSPI0_D4 | Disable | NA | 0 | Enable | 0 | PADCONFIG7 |
| OSPI0_D5 | OSPI0_D5 | Disable | NA | 0 | Enable | 0 | PADCONFIG8 |
| OSPI0_D6 | OSPI0_D6 | Disable | NA | 0 | Enable | 0 | PADCONFIG9 |
| OSPI0_D7 | OSPI0_D7 | Disable | NA | 0 | Enable | 0 | PADCONFIG10 |
| OSPI0_CSn0 | OSPI0_CSn0 | Disable | NA | 0 | Disable | 0 | PADCONFIG11 |
| OSPI0_CSn1 | OSPI0_CSn1 | Disable | NA | 0 | Disable | 0 | PADCONFIG12 |