SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
IR-IrDA and IR-CIR modes only.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 003Ch |
| UART1 | 0281 003Ch |
| UART2 | 0282 003Ch |
| UART3 | 0283 003Ch |
| UART4 | 0284 003Ch |
| UART5 | 0285 003Ch |
| UART6 | 0286 003Ch |
| WKUP_UART0 | 2B30 003Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PULSE_TYPE | SD_MOD | DIS_IR_RX | DIS_TX_UNDERRUN | SEND_SIP | SCTX_EN | ABORT_EN | EOT_EN |
| R/W | R/W | R/W | R/W | R/W1TS | R/W1TS | R/W | R/W1TS |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7 | PULSE_TYPE | R/W | 0h | SIR pulse width select: 0 3/16 of baud-rate pulse width 1 1.6us |
| 6 | SD_MOD | R/W | 0h | Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 SD pin is set to high 1 SD pin is set to low |
| 5 | DIS_IR_RX | R/W | 0h | 0 Normal operation (RX input automatically
disabled during transmit but enabled
outside of transmit operation).
1 Disables RX input (permanent state -
independent of transmit). |
| 4 | DIS_TX_UNDERRUN | R/W | 0h | It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1, garbage data is sent over TX line. 0 Long stop bits cannot be transmitted, TX
underrun is enabled
1 Long stop bits can be transmitted, TX
underrun is disabled |
| 3 | SEND_SIP | R/W1TS | 0h | MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]
If this bit is set during a MIR/FIR transmission, the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 No action 1 Send SIP pulse. |
| 2 | SCTX_EN | R/W1TS | 0h | Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing. Reset Source: mod_g_arstn |
| 1 | ABORT_EN | R/W | 0h | Frame Abort. The LH can intentionally abort transmission of a frame by Writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1, UART IrDA will start a new transfer with data of previous frame as soon as abort frame has been sent. Therefore, TX FIFO must be reset before sending an abort frame. Reset Source: mod_g_arstn |
| 0 | EOT_EN | R/W1TS | 0h | EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]. Reset Source: mod_g_arstn |