The ARM Cortex-R5F processor subsystem (R5FSS) supports the following main features:
- Armv7-R architecture
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R5FSS Memory System
- 32KB Instruction Cache
- 4x8KB ways
- SECDED ECC protected per 64 bits
- 32KB Data Cache
- 64KB tightly-coupled memory (TCM) per CPU
- SECDED ECC protected per 32 bits
- TCM hard error cache Implemented in CPU
- Readable/writable from system
- TCMs initialized (to 0's) at reset
- 32KB TCMA (ATCM)
- 16KB TCMB0 (B0TCM)
- 16KB TCMB1 (B1TCM)
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Full-precision Floating Point (VFPv3)
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16-region Memory Protection Unit (MPU)
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8 breakpoints, 8 watch points
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CoreSight Debug Access Port (DAP)
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CoreSight ETM-R5 interface (CTI, ETM)
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Performance Monitoring Unit (PMU)
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32-bit to 36-bit Region-based Address Translation (RAT) on memory access initiators
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Integrated Vectored Interrupt Manager (VIM) per core with 256 Interrupt Inputs each
- Programmable interrupt priority (4-bit)
- Programmable interrupt enable mask
- Software-generated interrupts
- Synchronous clock domain crossing on all core interfaces
- MAIN Domain R5FSSs are dual core and are also known as MCUSS
Note:
CORE0 has 64KB of TCM.
Note: These details describe a superset of the R5FSS memory configuration. For additional details on device memory availability, please refer to the device-specific Datasheet.