SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The error interrupt is used to signal a FIFO error condition. Below is a list of events that will cause the error interrupt to fire:
Overflow and underflow status for each SRC channel can be read through the ASRC_SRCFFCTRL_0 register. Clearing ERROR_INTR also clears the overflow/underflow status for that channel.