SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the controls for serial indrect access and trace processing
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3404 0004h |
| C7X256V1_DEBUG | 0007 3804 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD1 | CONTINUOUS_READ_NUM | CONTINUOUS_READ_MODE | |||||
| R | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0 | TRACE_EN | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:11 | RSVD1 | R | 0h | rsvd1 Reset Source: cfg_rst_n |
| 10:9 | CONTINUOUS_READ_NUM | R/W | 0h | continuous read num Reset Source: cfg_rst_n |
| 8 | CONTINUOUS_READ_MODE | R/W | 0h | continuous read mode Reset Source: cfg_rst_n |
| 7:1 | RSVD0 | R | 0h | rsvd0 Reset Source: cfg_rst_n |
| 0 | TRACE_EN | R/W | 0h | trace enable Reset Source: cfg_rst_n |