SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Single ended receivers threshold trimming
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 8048h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RX_ANA_REG5 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7:0 | RX_ANA_REG5 | R/W | 0h | Bits 7:3= reserved. Bits 2:1= 01 Switching thresholds for single ended receivers increased by 100mV, 10 Switching thresholds for single ended receivers reduced by 100mV. Bit 0= 0 Default Switching Thresholds for Single ended receivers, 1 SERx Switching Thresholds are controlled by bits [2:1]. Reset Source: usb2_sync_preset_n |