SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Use to manually set the TX DMA threshold level. MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size). If not, 64-tx_trigger_level will be used w/o modifying the value of this register.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0084h |
| UART1 | 0281 0084h |
| UART2 | 0282 0084h |
| UART3 | 0283 0084h |
| UART4 | 0284 0084h |
| UART5 | 0285 0084h |
| UART6 | 0286 0084h |
| WKUP_UART0 | 2B30 0084h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TX_DMA_THRESHOLD | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED1 | R | 0h | RESERVED |
| 7:6 | RESERVED | R | 0h | Reserved |
| 5:0 | TX_DMA_THRESHOLD | R/W | 0h | Use to manually set the TX DMA threshold level. Reset Source: mod_g_arstn |