SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Provides Aggregated, Read Only status of access error interrupts reported by MMR components.. Processors on the SoC read this MMR to determine which MMR components require service. Actual service of MMR interrupts must be handled through each MMR component.
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4300 0280h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | ACCESS_ERR_STAT_ACCESS_ERR_IN9 | ACCESS_ERR_STAT_ACCESS_ERR_IN8 | |||||
| NONE | R | R | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ACCESS_ERR_STAT_ACCESS_ERR_IN4 | ACCESS_ERR_STAT_ACCESS_ERR_IN3 | RESERVED | ACCESS_ERR_STAT_ACCESS_ERR_IN0 | |||
| NONE | R | R | NONE | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:10 | RESERVED | NONE | 0h | Reserved |
| 9 | ACCESS_ERR_STAT_ACCESS_ERR_IN9 | R | 0h | Access Error Detected in MCU PadCfg MMR Field values (others are reserved): 1'b0 - INACTIVE 1'b1 - ACTIVE Reset Source: mod_por_rst_n |
| 8 | ACCESS_ERR_STAT_ACCESS_ERR_IN8 | R | 0h | Access Error Detected in MCU Ctrl MMR Field values (others are reserved): 1'b0 - INACTIVE 1'b1 - ACTIVE Reset Source: mod_por_rst_n |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4 | ACCESS_ERR_STAT_ACCESS_ERR_IN4 | R | 0h | Access Error Detected in MAIN PadCfg MMR Field values (others are reserved): 1'b0 - INACTIVE 1'b1 - ACTIVE Reset Source: mod_por_rst_n |
| 3 | ACCESS_ERR_STAT_ACCESS_ERR_IN3 | R | 0h | Access Error Detected in MAIN Ctrl MMR Field values (others are reserved): 1'b0 - INACTIVE 1'b1 - ACTIVE Reset Source: mod_por_rst_n |
| 2:1 | RESERVED | NONE | 0h | Reserved |
| 0 | ACCESS_ERR_STAT_ACCESS_ERR_IN0 | R | 0h | Access Error Detected in WKUP Ctrl MMR Field values (others are reserved): 1'b0 - INACTIVE 1'b1 - ACTIVE Reset Source: mod_por_rst_n |