SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Enables PBIST Config Modes access to memories
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4300 C400h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PBIST_EN_MAIN_R5SS1 | PBIST_EN_MAIN_R5SS0 | RESERVED | PBIST_EN_AASRC1 | PBIST_EN_AASRC0 | ||
| NONE | R/W | R/W | NONE | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PBIST_EN_USB0 | RESERVED | PBIST_EN_EMMC0 | ||||
| NONE | R/W | NONE | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:22 | RESERVED | NONE | 0h | Reserved |
| 21 | PBIST_EN_MAIN_R5SS1 | R/W | 0h | Enables PBIST Access to Main R5SS1 Memories Field values (others are reserved): 1'b0 - DISABLE 1'b1 - ENABLE Reset Source: mod_g_rst_n |
| 20 | PBIST_EN_MAIN_R5SS0 | R/W | 0h | Enables PBIST Access to Main R5SS0 Memories Field values (others are reserved): 1'b0 - DISABLE 1'b1 - ENABLE Reset Source: mod_g_rst_n |
| 19:18 | RESERVED | NONE | 0h | Reserved |
| 17 | PBIST_EN_AASRC1 | R/W | 0h | Enables PBIST Access to AASRC1 Memories Field values (others are reserved): 1'b0 - DISABLE 1'b1 - ENABLE Reset Source: mod_g_rst_n |
| 16 | PBIST_EN_AASRC0 | R/W | 0h | Enables PBIST Access to AASRC0 Memories Field values (others are reserved): 1'b0 - DISABLE 1'b1 - ENABLE Reset Source: mod_g_rst_n |
| 15:5 | RESERVED | NONE | 0h | Reserved |
| 4 | PBIST_EN_USB0 | R/W | 0h | Enables PBIST Access to USB0 Memories Field values (others are reserved): 1'b0 - DISABLE 1'b1 - ENABLE Reset Source: mod_g_rst_n |
| 3:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PBIST_EN_EMMC0 | R/W | 0h | Enables PBIST Access to MMC0 Memories Field values (others are reserved): 1'b0 - DISABLE 1'b1 - ENABLE Reset Source: mod_g_rst_n |