SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Configures and enables LBIST operation
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 C000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| R5SS0_LBIST_CTRL_BIST_RESET | RESERVED | R5SS0_LBIST_CTRL_BIST_RUN | |||||
| R/W | NONE | R/W | |||||
| 0h | 0h | 0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| R5SS0_LBIST_CTRL_RUNBIST_MODE | RESERVED | R5SS0_LBIST_CTRL_DC_DEF | |||||
| R/W | NONE | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R5SS0_LBIST_CTRL_LOAD_DIV | RESERVED | R5SS0_LBIST_CTRL_DIVIDE_RATIO | |||||
| R/W | NONE | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | R5SS0_LBIST_CTRL_BIST_RESET | R/W | 0h | Reset LBIST macro Reset Source: mod_g_rst_n |
| 30:28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | R5SS0_LBIST_CTRL_BIST_RUN | R/W | 0h | Starts LBIST if all bits are 1 Reset Source: mod_g_rst_n |
| 23:16 | RESERVED | NONE | 0h | Reserved |
| 15:12 | R5SS0_LBIST_CTRL_RUNBIST_MODE | R/W | 0h | Runbist mode enable if all bits are 1 Reset Source: mod_g_rst_n |
| 11:10 | RESERVED | NONE | 0h | Reserved |
| 9:8 | R5SS0_LBIST_CTRL_DC_DEF | R/W | 0h | Clock delay after scan_enable switching Reset Source: mod_g_rst_n |
| 7 | R5SS0_LBIST_CTRL_LOAD_DIV | R/W | 0h | Loads LBIST clock divide ratio on transition from 0 to 1 Reset Source: mod_g_rst_n |
| 6:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | R5SS0_LBIST_CTRL_DIVIDE_RATIO | R/W | 0h | LBIST clock divide ratio Reset Source: mod_g_rst_n |