SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This is a control register. One register per power domain.
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| Instance Name | Physical Address |
|---|---|
| WKUP_PSC0 | 0400 0300h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| FORCE | RESERVED | PWRSW | ISO | RESERVED | |||
| R/W | NONE | R/W | R/W | NONE | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| WAKECNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PDMODE | RESERVED | EMUIHBIE | EPCGOOD | |||
| NONE | R/W | NONE | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NEXT | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | FORCE | R/W | 0h | Force Bit Reset Source: chip_rst.chip_1_rst_n |
| 30 | RESERVED | NONE | 0h | Reserved |
| 29 | PWRSW | R/W | 0h | Power shorting Switch Control Reset Source: chip_rst.chip_1_rst_n |
| 28 | ISO | R/W | 0h | Isolation Cell control Reset Source: chip_rst.chip_1_rst_n |
| 27:24 | RESERVED | NONE | 0h | Reserved |
| 23:16 | WAKECNT | R/W | 0h | RAM wake count delay value Reset Source: chip_rst.chip_1_rst_n |
| 15 | RESERVED | NONE | 0h | Reserved |
| 14:12 | PDMODE | R/W | 0h | Power Down mode 0 Core Off, RAM Array Off, RAM Periphery Off
8 Core Retention, RAM Array Off, RAM
Periphery Off
9 Core Retention, RAM Array Retention, RAM
Periphery Off
10 Core On, RAM Array Retention, RAM Periphery
Off
11 Core On, RAM Array Retention, RAM Periphery
On
15 Core On, RAM Array On, RAM Periphery On |
| 11:10 | RESERVED | NONE | 0h | Reserved |
| 9 | EMUIHBIE | R/W | 0h | Emulation alters domain state 0 Not enabled 1 Interrupt enabled |
| 8 | EPCGOOD | R/W | 0h | External Power Control Power Good Indication Reset Source: chip_rst.chip_1_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | NEXT | R/W | 0h | User_Desired Next Power Domain State 0 Off 1 On |