SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to program the software reset for data, command and for all
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 002Fh |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | SWRST_FOR_DAT | SWRST_FOR_CMD | SWRST_FOR_ALL | ||||
| NONE | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7:3 | RESERVED | NONE | 0h | Reserved |
| 2 | SWRST_FOR_DAT | R/W | 0h |
Only part of data circuit is reset. The following registers and bits are cleared by this bit:
Buffer Data Port Register: Buffer is cleared and Initialized.
Present State register:
Buffer read Enable,
Buffer write Enable,
Read Transfer Active,
Write Transfer Active,
DAT Line Active,
Command Inhibit [DAT].
Block Gap Control register:
Continue Request,
Stop At Block Gap Request.
Normal Interrupt Status register:
Buffer Read Ready,
Buffer Write Ready,
Block Gap Event,
Transfer Complete.
1 0 |
| 1 | SWRST_FOR_CMD | R/W | 0h |
Software Reset For CMD Line Only part of command circuit is reset to be able to issue a command. From Version 4.10, this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit [including response error statuses related to Com-mand Inhibit [CMD] control] and does not affect data transfer circuit. Host Controller can continue data transfer even this reset is executed during handling of sub com- mand response errors. The following registers and bits are cleared by this bit: Present State register Command Inhibit [CMD] Normal Interrupt Status register Command Complete Error Interrupt Status [from Version 4.10] Response error statuses related to Com-mand Inhibit [CMD]
1 0 |
| 0 | SWRST_FOR_ALL | R/W | 0h |
This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when capabilities registers are valid and the HD can read them. Additional use of Software Reset For All may not affect the value of the Capabilities registers. If this bit is set to 1, the SD card shall reset itself and must be re initialized by the HD.
1 0 |