SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
In compare block active mode, the output signals of CPU1 (after clamping) are compared against their clamped values, and a mismatch is indicated by the bus monitor error signal. Additionally, as indicated in Table 7-8, the self test error signal is also asserted.
The self test error signal is shared by both the CCMR5's CPU compare and inactivity monitor blocks.