SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The ASRC_SYS_CLK is used for all filter processing in the module..
The ASRC_VBUS_CLK is used for VBUS interfaces.
There are four dividers present to divide the input audio sample rate clocks (ASRC_RXSYNC0-7 and ASRC_TXSYNC0-7). Two dividers are used for RX side and other two dividers are used for the TX side. The RX side dividers are working on the muxed ASRC_RXSYNC0-7 clocks. The TX side dividers are working on the muxed ASRC_TXSYNC0-7 clocks. The dividers are used for Clock Zone 0 and Clock Zone 1 only, on both RX and TX sides, and are controlled via ASRC_ICKDIV register (for RX side) and ASRC_OCKDIV register (for TX side).
The muxing of ASRC_RXSYNC0-7 clocks is controlled by [3-0] INPUT_CLOCK_ZONE_CLOCK_SOURCE_SELECT bit-field within ASRC_ICKZCTRL_0 to ASRC_ICKZCTRL_3 registers. The muxing of ASRC_TXSYNC0-7 clocks is controlled by [3-0] OUTPUT_CLOCK_ZONE_CLOCK_SOURCE_SELECT bit-field within ASRC_OCKZCNT_0 to ASRC_OCKZCNT_3 registers.
Figure 12-3 ASRC Input and Output Clock Zone Controls