SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
refclock selection
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 811Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UNUSED | REFCLK_SEL | REFCLK_SEL_EN | |||||
| R/W | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7:5 | UNUSED | R/W | 0h | unused Reset Source: usb2_sync_preset_n |
| 4:1 | REFCLK_SEL | R/W | 0h | 0000 Refclock selection for 9.6 MHz, 0001 Refclock selection for 10 MHz, 0010 Refclock selection for 12 MHz, 0011 Refclock selection for 19.2 MHz, 0100 Refclock selection for 20 MHz, 0101 Refclock selection for 24 MHz, 0110 Refclock selection for 25 MHz, 0111 Refclock selection for 26 MHz, 1000 Refclock selection for 38.4 MHz, 1001 Refclock selection for 40 MHz, 1010 Refclock selection for 48 MHz, 1011 Refclock selection for 50 MHz, 1100 Refclock selection for 52 MHz, 1101 Refclock selection for 9.6 MHz, 1110 Refclock selection for 9.6 MHz, 1111 Refclock selection for 9.6 MHz. Reset Source: usb2_sync_preset_n |
| 0 | REFCLK_SEL_EN | R/W | 0h | 0 PLLREFSEL Value not taken from PLL_REG7[4:1], 1 PLLREFSEL Value taken from PLL_REG7[4:1]. Reset Source: usb2_sync_preset_n |