SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the hardware configuration options
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C150h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| GHWPARAMS4_31_28 | GHWPARAMS4_27_24 | ||||||
| R | R | ||||||
| 4h | 7h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| GHWPARAMS4_23 | GHWPARAMS4_22 | GHWPARAMS4_21 | GHWPARAMS4_20_17 | GHWPARAMS4_16_13 | |||
| R | R | R | R | R | |||
| 1h | 0h | 1h | 1h | 1h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| GHWPARAMS4_16_13 | GHWPARAMS4_12 | GHWPARAMS4_11 | GHWPARAMS4_10_9 | GHWPARAMS4_8_7 | |||
| R | R | R | R | R | |||
| 1h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GHWPARAMS4_8_7 | GHWPARAMS4_6 | GHWPARAMS4_5_0 | |||||
| R | R | R | |||||
| 0h | 0h | 4h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | GHWPARAMS4_31_28 | R | 4h | DWC_USB3_BMU_LSP_DEPTH Reset Source: rst_mod_g_rst_n |
| 27:24 | GHWPARAMS4_27_24 | R | 7h | DWC_USB3_BMU_PTL_DEPTH-1 Reset Source: rst_mod_g_rst_n |
| 23 | GHWPARAMS4_23 | R | 1h | DWC_USB3_EN_ISOC_SUPT Reset Source: rst_mod_g_rst_n |
| 22 | GHWPARAMS4_22 | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 21 | GHWPARAMS4_21 | R | 1h | DWC_USB3_EXT_BUFF_CONTROL Reset Source: rst_mod_g_rst_n |
| 20:17 | GHWPARAMS4_20_17 | R | 1h | DWC_USB3_NUM_SS_USB_INSTANCES Reset Source: rst_mod_g_rst_n |
| 16:13 | GHWPARAMS4_16_13 | R | 1h | DWC_USB3_HIBER_SCRATCHBUFS Number of external scratchpad buffers the controller requires to save its internal state in the device mode. Each buffer is assumed to be 4KB. The scratchpad buffer array must have this many buffer pointers. Reset Source: rst_mod_g_rst_n |
| 12 | GHWPARAMS4_12 | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 11 | GHWPARAMS4_11 | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 10:9 | GHWPARAMS4_10_9 | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 8:7 | GHWPARAMS4_8_7 | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 6 | GHWPARAMS4_6 | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 5:0 | GHWPARAMS4_5_0 | R | 4h | DWC_USB3_CACHE_TRBS_PER_TRANSFER Reset Source: rst_mod_g_rst_n |