SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
For detailed DCC compute calculations, refer to Continuous Monitor of the PLL Frequency With the DCC App Note.
The DCC has two parallel counters that count clock pulses for two independent clock sources:
The error signal is generated by any one of the following conditions:
Any of these errors causes the counters to stop counting. An application must then read out the counter values to determine what caused the error. Once the error is detected, the counters are stopped after 3 FICLK and 2 source clock cycles due to the cross clock domain synchronisation.
Reloads or restarts occur under two conditions:
The DCC module does not check jitter for Clock0 or Clock1.
As the counter preset signal is synchronized to either of the source clock domains, the counters begin downcounting after two corresponding source clock cycles.
The error signal is captured to the FICLK domain. There is 1 FICLK period uncertainty on either side of the fixed width counting window (VALID0) in generating the error signal since the counters work in different clock domains. This should be accounted for when setting the count value for VALID0.
Figure 12-370 through Figure 12-374 shows examples of counters relationship and error generation.
Figure 12-370 DCC
Clock0 and Clock1 With no Error
Figure 12-371 DCC
Clock1 slower than Clock0 results in an error and
stops counting
Figure 12-372 DCC
Clock1 faster than Clock0 results in an error and
stops counting
Figure 12-373 DCC
Clock1 not present results in an error and stops
counting
Figure 12-374 DCC
Clock0 not present results in an error and stops
counting