The streaming engine (SE) supports the
following key features:
- Provides a flexible, high
bandwidth mechanism for reading large quantities of data into C7x CPU
- Supplies two 256-bit data streams
(S0, S1) directly from L2 to the vector units
- Provides two stream address
generators, supporting the two data streams
- Flexible
multi-dimensional address calculators
- Provide offset addresses
for load and store instructions
- Supports element promotion,
decimation, duplication, transpose loads, predication
- LEZR feature can be enabled to
return N number of zero vectors to CPU after selected dimension ends. LEZR and
transposed mode are not supported together. LEZR is still supported when
transposed mode is disabled..
- Provides 6D addressing
- Access patterns up to 6D
can be programmed ahead
- 6D data is presented as
512-bit vector per cycle
- Communicates with L2 memory
controller for requests beyond L2 (MSMC, DDR)
- Coherent with L1D data at stream
open/close boundaries
- ECC SECDED support
The SE can sustain 512-bits/cycle
total bandwidth (256 bits/cycle on each of two streams) to the DSP CPU. When
combined with its 256-bit/cycle vector load unit and 256-bit/cycle store unit, the
DSP CPU can access 1024 bits/cycle of data.