SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This is the value of the rate for the clock generator 2. This contains the upper 16 bits of the integer and the enable for the clock generator. This register is used to generate soft clock
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| Instance Name | Physical Address |
|---|---|
| AASRC0 | 02D0 030Ch |
| AASRC1 | 02D4 030Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| INPUT_CLK_GEN_EN | RESERVED | ||||||
| R/W | R | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RATE_INT_HI | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RATE_INT_HI | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | INPUT_CLK_GEN_EN | R/W | 0h | This signal enables the Input Clock Generator 2 0 Clock generator disabled 1 Clock generator enabled |
| 30:16 | RESERVED | R | 0h | Always read as 0 |
| 15:0 | RATE_INT_HI | R/W | 0h | This is the lower 8 bits of the integer multiple of the rate for the clock source This register will be added with the Clock Generator Stamp to update the Stamp value whenever the Free Running Counter passes the Stamp value |