SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Selects the source signal for the ASRC0 RXSYNC3 frame sync input
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 A4CCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ASRC0_RXSYNC3_SEL_SYNC_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | ASRC0_RXSYNC3_SEL_SYNC_SEL_PROXY | R/W | 0h | RXSYNC source signal Field values (others are reserved): 5'b00000 - McASP0 AFSR Pin Input 5'b00001 - McASP1 AFSR Pin Input 5'b00010 - McASP2 AFSR Pin Input 5'b00011 - McASP3 AFSR Pin Input 5'b00100 - McASP4 AFSR Pin Input 5'b00101 - '0' - Reserved 5'b00110 - '0' - Reserved 5'b00111 - '0' - Reserved 5'b01000 - McASP0 AFSX Pin Input 5'b01001 - McASP1 AFSX Pin Input 5'b01010 - McASP2 AFSX Pin Input 5'b01011 - McASP3 AFSX Pin Input 5'b01100 - McASP4 AFSX Pin Input 5'b01101 - '0' - Reserved 5'b01110 - '0' - Reserved 5'b01111 - '0' - Reserved 5'b10000 - AUDIO_EXT_REFCLK0 Pin input 5'b10001 - AUDIO_EXT_REFCLK1 Pin input 5'b10010 - AUDIO_EXT_REFCLK2 Pin input 5'b10011 - '0' - Reserved 5'b10100 - ADC0_CLK 5'b10101 - MLB_IO_CLK 5'b10110 - MAIN_PLL4_HSDIV3_CLKOUT 5'b10111 - '0' - Reserved 5'b11000 - MCU_EXT_REFCLK0 Pin 5'b11001 - EXT_REFCLK1 Pin 5'b11010 - CPSW_CPTS_GENF0 5'b11011 - CPSW_CPTS_GENF1 5'b11100 - '0' - Reserved 5'b11101 - '0' - Reserved 5'b11110 - '0' - Reserved 5'b11111 - '0' - Reserved Reset Source: mod_g_rst_n |