SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to set attributes on the VBUSM memory accesses and to read the Debug Operating Mode
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| Instance Name | Physical Address |
|---|---|
| DEBUGSS_WRAP0 | 0007 6000 2010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DOM_INPUT | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DOM_INPUT | RESERVED | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VBUSM_PRIV | VBUSM_SECURE | VBUSM_DEBUG | CTL_PRIV | CTL_SECURE | EMUDBG | ||
| R | R | R | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:21 | DOM_INPUT | R | 0h | This returns the DOM security input The upper 3 bits are the debug operating mode and the lower 8 bits are the priviledge ID for VBUSM transaction |
| 20:8 | RESERVED | R | 0h | Reserved bits, return 0 |
| 7:6 | VBUSM_PRIV | R | 0h | These two bits show the currently state of the priv bits |
| 5 | VBUSM_SECURE | R | 0h | This bit shows the currently active state of the VBUSM secure bit |
| 4 | VBUSM_DEBUG | R | 0h | This is the currently active state of the VBUSM emudbg bit |
| 3:2 | CTL_PRIV | R/W | 0h | These two bits determine the priviledge type for VBUSM accesses unless overridden by the DOM input [0 is user level privilege, 1 is supervisor level privilege, 2 is hypervisor level privilege and 3 is reserved] |
| 1 | CTL_SECURE | R/W | 0h | When set [and DOM permits it], the VBUSM accesses will have the secure bit set |
| 0 | EMUDBG | R/W | 0h | Sets the emudbg bit during access to make the debug or non-debug |