SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register configures the FIFO settings for Group 1.
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| Instance Name | Physical Address |
|---|---|
| AASRC0 | 02D0 0188h |
| AASRC1 | 02D4 0188h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | R_CHANNEL_OUTFIFO_UNDERFLOW | L_CHANNEL_OUTFIFO_UNDERFLOW | R_CHANNEL_OUTFIFO_OVERFLOW | L_CHANNEL_OUTFIFO_OVERFLOW | |||
| R | R | R | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| OUTFIFO_THRESHOLD | |||||||
| R/W | |||||||
| 1h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | R_CHANNEL_INFIFO_UNDERFLOW | L_CHANNEL_INFIFO_UNDERFLOW | R_CHANNEL_INFIFO_OVERFLOW | L_CHANNEL_INFIFO_OVERFLOW | |||
| R | R | R | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INFIFO_THRESHOLD | |||||||
| R/W | |||||||
| 1h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | R | 0h | Always read as 0 |
| 27 | R_CHANNEL_OUTFIFO_UNDERFLOW | R | 0h | This signal is set to 1 when any of the Right Channel OUTFIFO for Group1 SRCs is underflowed 0 No underflow is detected 1 Underflow is detected |
| 26 | L_CHANNEL_OUTFIFO_UNDERFLOW | R | 0h | This signal is set to 1 when any of the Left Channel OUTFIFO for Group1 SRCs is underflowed 0 No underflow is detected 1 Underflow is detected |
| 25 | R_CHANNEL_OUTFIFO_OVERFLOW | R | 0h | This signal is set to 1 when any of the Right Channel OUTFIFO for Group1 SRCs is overflowed 0 No overflow is detected 1 Overflow is detected |
| 24 | L_CHANNEL_OUTFIFO_OVERFLOW | R | 0h | This signal is set to 1 when any of the Left Channel OUTFIFO for Group1 SRCs is overflowed 0 No overflow is detected 1 Overflow is detected |
| 23:16 | OUTFIFO_THRESHOLD | R/W | 1h | This is the number of samples that must be available for the interrupt and Group1 SRCs OUTFIFOs event to fire |
| 15:12 | RESERVED1 | R | 0h | Always read as 0 |
| 11 | R_CHANNEL_INFIFO_UNDERFLOW | R | 0h | This signal is set to 1 when any of the Right Channel INFIFO for Group1 SRCs is underflowed 0 No underflow is detected 1 Underflow is detected |
| 10 | L_CHANNEL_INFIFO_UNDERFLOW | R | 0h | This signal is set to 1 when any of the Left Channel INFIFO for Group1 SRCs is underflowed 0 No underflow is detected 1 Underflow is detected |
| 9 | R_CHANNEL_INFIFO_OVERFLOW | R | 0h | This signal is set to 1 when any of the Right Channel INFIFO for Group1 SRCs is overflowed 0 No overflow is detected 1 Overflow is detected |
| 8 | L_CHANNEL_INFIFO_OVERFLOW | R | 0h | This signal is set to 1 when any of the Left Channel INFIFO for Group1 SRCs is overflowed 0 No overflow is detected 1 Overflow is detected |
| 7:0 | INFIFO_THRESHOLD | R/W | 1h | This is the number of samples that must be available for the interrupt and Group1 SRCs INFIFOs event to fire |