SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Time Base Counter Register
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| Instance Name | Physical Address |
|---|---|
| EPWM0 | 2300 0008h |
| EPWM1 | 2301 0008h |
| EPWM2 | 2302 0008h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TBCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TBCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:0 | TBCNT | R/W | 0h | Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register is not shadowed |