SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controls ADC0 calibration sequence (not used)
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 64F0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADC0_CAL_CAL_EN_PROXY | ADC0_CAL_DIFF_CAL_EN_PROXY | RESERVED | |||||
| R/W | R/W | NONE | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ADC0_CAL_CAL_CAP_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15 | ADC0_CAL_CAL_EN_PROXY | R/W | 0h | Enable single-ended calibration Set to 1 to begin single-ended calibration Reset Source: mod_g_rst_n |
| 14 | ADC0_CAL_DIFF_CAL_EN_PROXY | R/W | 0h | Enable differential calibration Set to 1 to begin differential calibration Reset Source: mod_g_rst_n |
| 13:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | ADC0_CAL_CAL_CAP_SEL_PROXY | R/W | 0h | Select capacitor for calibration Bits correspond to C5:C1 Reset Source: mod_g_rst_n |