SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Selects additional divide value for the MAIN_PLL4 clock source to the ASRC RXSYNC and TXSYNC selection muxes
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 A2F0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | ASRC_SYNC_DIV_CTRL_CLK_DIV_LD_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ASRC_SYNC_DIV_CTRL_CLK_DIV_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED | NONE | 0h | Reserved |
| 8 | ASRC_SYNC_DIV_CTRL_CLK_DIV_LD_PROXY | R/W | 0h | Load the divider value Writing 1 to this bit will generate a load pulse to load the clk_div divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed. Field values (others are reserved): 1'b0 - READY 1'b1 - LOAD Reset Source: mod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | ASRC_SYNC_DIV_CTRL_CLK_DIV_PROXY | R/W | 0h | ASRC Sync divider value Divides MAIN_PLL4_HSDIV_CLKOUT3 by clkdiv+1. Supports divide by 1 to 16 (default to 1). To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Reset Source: mod_g_rst_n |