SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controls the functional clock source for MCAN2
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 A488h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MCAN2_CLKSEL_CLK_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | MCAN2_CLKSEL_CLK_SEL_PROXY | R/W | 0h | MCAN functional clock selection Field values (others are reserved): 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 (Pin) 2'b10 - EXT_REFCLK1 (Pin) 2'b11 - HFOSC0_CLKOUT Reset Source: sys_por_rst_n |